system chip

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Published By: Wave Computing     Published Date: Jul 06, 2018
This paper argues a case for the use of coarse grained reconfigurable array (CGRA) architectures for the efficient acceleration of the data flow computations used in deep neural network training and inferencing. The paper discusses the problems with other parallel acceleration systems such as massively parallel processor arrays (MPPAs) and heterogeneous systems based on CUDA and OpenCL, and proposes that CGRAs with autonomous computing features deliver improved performance and computational efficiency. The machine learning compute appliance that Wave Computing is developing executes data flow graphs using multiple clock-less, CGRA-based System on Chips (SoCs) each containing 16,000 processing elements (PEs). This paper describes the tools needed for efficient compilation of data flow graphs to the CGRA architecture, and outlines Wave Computing’s WaveFlow software (SW) framework for the online mapping of models from popular workflows like Tensorflow, MXNet and Caffe.
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Wave Computing
Published By: Oracle CX     Published Date: Oct 19, 2017
Oracle has just announced a new microprocessor, and the servers and engineered system that are powered by it. The SPARC M8 processor fits in the palm of your hand, but it contains the result of years of co-engineering of hardware and software together to run enterprise applications with unprecedented speed and security. The SPARC M8 chip contains 32 of today’s most powerful cores for running Oracle Database and Java applications. Benchmarking data shows that the performance of these cores reaches twice the performance of Intel’s x86 cores. This is the result of exhaustive work on designing smart execution units and threading architecture, and on balancing metrics such as core count, memory and IO bandwidth. It also required millions of hours in testing chip design and operating system software on real workloads for database and Java. Having faster cores means increasing application capability while keeping the core count and software investment under control. In other words, a boost
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Oracle CX
Published By: Oracle CX     Published Date: Oct 20, 2017
Oracle has just announced a new microprocessor, and the servers and engineered system that are powered by it. The SPARC M8 processor fits in the palm of your hand, but it contains the result of years of co-engineering of hardware and software together to run enterprise applications with unprecedented speed and security. The SPARC M8 chip contains 32 of today’s most powerful cores for running Oracle Database and Java applications. Benchmarking data shows that the performance of these cores reaches twice the performance of Intel’s x86 cores. This is the result of exhaustive work on designing smart execution units and threading architecture, and on balancing metrics such as core count, memory and IO bandwidth. It also required millions of hours in testing chip design and operating system software on real workloads for database and Java. Having faster cores means increasing application capability while keeping the core count and software investment under control. In other words, a boost
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Oracle CX
Published By: Oracle PaaS/IaaS/Hardware     Published Date: Jul 25, 2017
"Oracle SPARC systems are engineered from the cloud and provide customers with effortless security, breakthrough efficiency, and straightforward simplicity. “Cloud is the way to go and we try to deliver that in the form of a platform that you can rely upon, that can scale, scale massively, scale reliably. The thing about SPARC in contract to other chips is the software that runs on it is highly reliable. You can heat it, you can beat it, you can give it a lot of load, but it doesn’t break, it just keeps running.”
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Oracle PaaS/IaaS/Hardware
Published By: Pure Storage     Published Date: Oct 09, 2017
Semiconductors run and connect today’s technology-driven world, powering all the electronic systems and products around us. Critical to communication, entertainment, work, medical diagnoses, travel, socializing, and making new discoveries, these specialized chips are ubiquitous. And chip designs grow ever more sophisticated in order to power new generations of devices, computers, the Internet, and the cloud. To enable new applications and use cases – like the Internet of Things – semiconductor vendors have continually pushed the boundaries of their designs to accommodate new fabrication processes that make chips smaller, more power efficient (to make personal devices last longer), and able to pack more gates into smaller dies (to make them more powerful).
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verification, storage, customer, innovation, management, pure storage
    
Pure Storage
Published By: Oracle     Published Date: Oct 20, 2017
Oracle has just announced a new microprocessor, and the servers and engineered system that are powered by it. The SPARC M8 processor fits in the palm of your hand, but it contains the result of years of co-engineering of hardware and software together to run enterprise applications with unprecedented speed and security. The SPARC M8 chip contains 32 of today’s most powerful cores for running Oracle Database and Java applications. Benchmarking data shows that the performance of these cores reaches twice the performance of Intel’s x86 cores. This is the result of exhaustive work on designing smart execution units and threading architecture, and on balancing metrics such as core count, memory and IO bandwidth. It also required millions of hours in testing chip design and operating system software on real workloads for database and Java. Having faster cores means increasing application capability while keeping the core count and software investment under control. In other words, a boost
Tags : 
    
Oracle
Published By: Oracle     Published Date: Oct 20, 2017
Oracle has just announced a new microprocessor, and the servers and engineered system that are powered by it. The SPARC M8 processor fits in the palm of your hand, but it contains the result of years of co-engineering of hardware and software together to run enterprise applications with unprecedented speed and security. The SPARC M8 chip contains 32 of today’s most powerful cores for running Oracle Database and Java applications. Benchmarking data shows that the performance of these cores reaches twice the performance of Intel’s x86 cores. This is the result of exhaustive work on designing smart execution units and threading architecture, and on balancing metrics such as core count, memory and IO bandwidth. It also required millions of hours in testing chip design and operating system software on real workloads for database and Java. Having faster cores means increasing application capability while keeping the core count and software investment under control. In other words, a boost
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Oracle
Published By: NComputing     Published Date: Oct 16, 2012
Download this white paper to read about how to best break through the long-running price/performance and manageability barriers to deliver a purpose-built endpoint solution for HDX.
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enterprise vdi, desktop virtualization, vdi deployment, virtual deployment, system-on-a-chip, enterprise applications, business technology, virtualization
    
NComputing
Published By: Borer Data Systems Ltd.     Published Date: Nov 07, 2007
At the Defcon security conference on August 2007, a hacker and Defcon staffer who goes by the name Zac Franken, showed how a small homemade device he calls "Gecko", which can perform a hack on the type of access card readers used on office doors throughout the country.
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security, security management, access control, identity management, iam, authentication, wiegand, tracking, workforce, workforce management, employee management, borer, access control, wiegand, security, borer, borer data systems, hacker, defcon, zac franken
    
Borer Data Systems Ltd.
Published By: Eran Glickman, Ron M. Bar, Benny Michalovich, Alankry Yaron     Published Date: May 26, 2011
A methodology to create multiple SoC using limited resources
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soc, system on chip, common frontend
    
Eran Glickman, Ron M. Bar, Benny Michalovich, Alankry Yaron
Published By: Freescale Semiconductor     Published Date: Jun 02, 2011
Aspects of functional verification of power aware security architecture
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power, system on chip, security
    
Freescale Semiconductor
Published By: Freescale Semiconductor     Published Date: Jul 07, 2011
An outline of the steps required to reach parallel test execution
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soc parallel verification
    
Freescale Semiconductor
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